I_data : in std_logic_vector(G_N-1 downto 0) Figure 2 Parallel to Serial conversion exampleĪn example of Parallel to Serial converter
The serializer section takes N clock cycles to output the serial data stream. The parallel input to the module shall be at a rate of less than or equal to 1/N clock cycles. Let assume the parallel data bus of the Parallel to Serial converter to be N bit. Parallel to Serial converter VHDL code example If you need to transfer 16-bit data 1MHz the serial data stream speed shall be at least greater than 16 x 1 MHz = 16 MHz. Same data rate you need to use a higher speed in data transfer. Figure 1 FPGA connection Parallel vs SerialĬould be to serialize the parallel data using less connection. As you can see, these are a lot of wires! Moreover, a skew between the bits in the parallel data bus can affect the connection integrity.
For instance, if we need to transfer a data bus of 16 bits between twoĭifferent FPGA at a rate of 1 MHz, we need to connect at leastġ6-bit data + 1 bit enable + 1 bit clock = 18 wires running 1 MHz. From two different devices, the simple way is to use the minimum numbers of
